| GNU Make Manual | www.imodulo.com · 2003-04-05 | ||
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To substitute a variable's value, write a dollar sign followed by the name of the variable in parentheses or braces: either $(foo) or ${foo} is a valid reference to the variable foo. This special significance of $ is why you must write $$ to have the effect of a single dollar sign in a file name or command.
Variable references can be used in any context: targets, prerequisites, commands, most directives, and new variable values. Here is an example of a common case, where a variable holds the names of all the object files in a program:
objects = program.o foo.o utils.o
program : $(objects)
cc -o program $(objects)
$(objects) : defs.h
Variable references work by strict textual substitution. Thus, the rule
foo = c
prog.o : prog.$(foo)
$(foo)$(foo) -$(foo) prog.$(foo)
could be used to compile a C program prog.c. Since spaces before the variable value are ignored in variable assignments, the value of foo is precisely c. (Don't actually write your makefiles this way!)
A dollar sign followed by a character other than a dollar sign, open-parenthesis or open-brace treats that single character as the variable name. Thus, you could reference the variable x with $x. However, this practice is strongly discouraged, except in the case of the automatic variables (Automatic Variables).
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